High voltage sensor device

ABSTRACT

In one embodiment, a high voltage element is formed overlying a doped semiconductor region that can be depleted during the operation of the high voltage element.

BACKGROUND OF THE INVENTION

The present invention relates, in general, to electronics, and moreparticularly, to methods of forming semiconductor devices and structure.

In the past, the semiconductor industry utilized various methods to formsemiconductor devices for controlling high voltage systems. One exampleof such a high voltage system was a power supply controller thatoperated from input voltages having high voltage values. One problemwith these prior semiconductor devices was an inability to sense thevalue of the high voltage in a continuous manner. Typically, externalcircuits were utilized to provide voltages that were representative ofthe value of the high voltage. For example, a controller may operatefrom an input voltage of several hundred volts and the value of thisvoltage may change with respect to time. In order to provide efficientoperation, the controller may need to sense the value of this voltage asit changes during the operation of the controller. The inability toproduce devices on a semiconductor chip that could be used to sense thevalue of the high voltage resulted in using the external componentswhich increased the cost of the system.

Accordingly, it is desirable to have a semiconductor device that cansense the value of a high voltage signal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 schematically illustrates a circuit diagram of an embodiment of aportion of a high voltage semiconductor device in accordance with thepresent invention;

FIG. 2 illustrates an enlarged plan view of an embodiment of a portionof the semiconductor device of FIG. 1 in accordance with the presentinvention;

FIG. 3 illustrates a cross-sectional portion of the embodiment of thesemiconductor device of FIG. 2 accordance with the present invention;

FIG. 4 schematically illustrates a circuit diagram of another embodimentof a portion of a high voltage semiconductor device in accordance withthe present invention;

FIG. 5 illustrates a an enlarged cross-sectional portion of anotherembodiment of a high voltage semiconductor device in accordance with thepresent invention;

FIG. 6 schematically illustrates a circuit diagram of an embodiment of aportion of a high voltage semiconductor device that is an alternateembodiment of the device of FIG. 1 in accordance with the presentinvention;

FIG. 7 illustrates an enlarged plan view of a portion of an embodimentof the high voltage semiconductor device of FIG. 6 in accordance withthe present invention; and

FIG. 8 schematically illustrates a circuit diagram of an embodiment of aportion of a system using the high voltage semiconductor device of FIG.1 in accordance with the present invention.

For simplicity and clarity of illustration, elements in the figures arenot necessarily to scale, and the same reference numbers in differentfigures denote the same elements. Additionally, descriptions and detailsof well-known steps and elements are omitted for simplicity of thedescription. As used herein current carrying electrode means an elementof a device that carries current through the device such as a source ora drain of an MOS transistor or an emitter or a collector of a bipolartransistor or a cathode or anode of a diode, and a control electrodemeans an element of the device that controls current through the devicesuch as a gate of an MOS transistor or a base of a bipolar transistor.Although the devices are explained herein as certain N-channel orP-Channel devices, a person of ordinary skill in the art will appreciatethat complementary devices are also possible in accordance with thepresent invention. For clarity of the drawings, doped regions of devicestructures are illustrated as having generally straight line edges andprecise angular corners. However, those skilled in the art understandthat due to the diffusion and activation of dopants the edges of dopedregions are generally not straight lines and the corners are not preciseangles.

DETAILED DESCRIPTION OF THE DRAWINGS

FIG. 1 schematically illustrates a circuit diagram of a preferredembodiment of a portion of a high voltage semiconductor device 10 thatforms a low voltage sense signal that is representative of an inputvoltage that has a high voltage value. Device 10 includes a high voltagesense element 11 that receives the high voltage and forms the sensesignal on a sense output 16 that is representative of the high voltage.As the value of the input voltage varies, the sense signal also varies.Device 10 also is formed to provide a first output current on a currentoutput 24 in response to control signals applied to a control input 25.

In one embodiment, element 11 is a portion of a high voltage transistorand sense device 28 of device 10 that is formed as a merged transistorincluding a JFET transistor 18 and a metal oxide semiconductor (MOS)transistor 19. Device 10 may also include a bias resistor 21 that isformed to provide bias currents to the gate of transistor 19.Transistors such as transistors 18 and 19 of device 28 are well known tothose skilled in the art. One example of a device similar to transistors18 and 19 is disclosed in U.S. Pat. No. 5,477,175 issued to Tisinger etal on Dec. 19, 1995 which is hereby incorporated herein by reference. Inother embodiments, transistor 19 may be other transistors structuressuch as a J-FET or a bipolar transistor. In other embodiments, resistor21 may be other structures such as a JEFT. Device 10 is formed toreceive the input voltage on a high voltage input 23 and generate thesense signal on output 16.

In the past, it was difficult to sense the value of a high voltage on asemiconductor device. For example, in some applications for world wideline voltage applications, the input voltage may exceed four hundredvolts (400 V) and in some cases could be as high as seven hundred volts(700 V). For example, flyback voltages of transformers used in powersupply systems can increase a four hundred volt input voltage to sevenhundred volts.

As will be seen further hereinafter, element 11 is formed in a mannerthat facilitates receiving such a high input voltage and responsivelyforming the sense signal. In one embodiment, element 11 is a resistordivider that is connected between input 23 and the lowest voltageapplied to the semiconductor device that incorporates element 11.Typically, the lowest voltage is a ground reference although othervalues may be used. The resistor divider includes a first resistor 12connected in series with a second resistor 13 with the sense signalformed at a common node at the common connection between the resistors.Only one terminal of resistor 12 is connected to a current carryingelectrode or terminal of either of transistors 18 and 19. The otherterminal or low voltage terminal of resistor 12 is not connected totransistors 18 and 19 but is connected to output 16 to facilitate adevice receiving the sense signal. Additionally, neither terminal ofresistor 13 is connected to a current carrying electrode of transistors18 and 19. Thus, a low voltage terminal of element 11 is not connectedto high voltage device 28 and transistors 18 and 19. Having only oneterminal connected to device 28 and transistors 18 and 19 assists inensuring that the sense signal has a low voltage. The value of resistors12 and 13 are selected to be large in order to minimize the powerdissipated by element 11. In one example embodiment, the totalresistance of the series combination of resistors 12 and 13 typically isno less than about fifteen (15) meg-ohms but may be other values inother embodiments.

In order to assist in providing the functionality of device 10, a drainof transistor 18 is commonly connected to input 23 and to a firstterminal 15 of element 11. A first terminal of resistor 12 is connectedto terminal 15 and a low voltage terminal of resistor 12 is connected tooutput 16. A connection terminal 14 of element 11 is connected to thelowest voltage of device 28. A first terminal of resistor 13 isconnected to output 16 and a second terminal is connected to terminal14. A source of transistor 18 is connected to a common node 20 and to adrain of transistor 19. A gate of transistor 19 is connected to input 25and to a first terminal of resistor 21, and a source is connected tooutput 24. A second terminal of resistor 21 is connected to node 20. Thegate connection of transistor 18 will be explained in more detail in thedescription of FIG. 2.

FIG. 2 illustrates an enlarged plan view of a portion of an embodimentof device 10 explained in the description of FIG. 1. FIG. 3 illustratesan enlarged cross-sectional portion of device 10 illustrated in FIG. 2along section line 3-3. This description has references to both FIG. 2and FIG. 3. Resistors 12 and 13 of element 11 are formed to overly aportion of J-FET 18 that is substantially depleted of carriers duringhigh voltage operation of transistor 18. The depleted portion oftransistor 18 allows element 11 to withstand the high voltage that isapplied to device 10 and form the sense signal on output 16.

Transistor 19 is identified in general by an arrow and dashed lines inFIG. 2. Transistors 18 and 19 generally are formed as closed geometricshapes on a surface of a semiconductor substrate 40. Typically theclosed geometric shapes have centers that are concentric and have someoverlapping periphery. In the preferred embodiment, the closed geometricshapes are formed as circles or arcs of circles having variousconcentric radii. For clarity of the explanation, the preferredembodiment is explained, however, those skilled in the art will realizethat other closed shapes such as ellipses, squares, pentagons, hexagons,inter-digitated fingers, etc. may also be used instead of circles andthat transistors 18 and 19 may have different lengths and widths.

In the preferred embodiment, the closed geometric shapes of transistor18 are formed as concentric circles that have increasing radii. A firstportion of the geometric shapes of transistor 19 are formed as a circleand a second portion are formed as arcs of a circle with the arcs havingradii that are larger than radii of the circle portion of transistor 18.A circular shaped doped region 41 is formed on a surface of a substrate40. In the preferred embodiment the doping profile of region 41 is not agraded profile that has multiple doping zones but is substantiallyconstant across region 41. Such a non-graded doping profile simplifiesmanufacturing and reduces manufacturing costs. It will be understoodthat the doping concentration may vary some due to depth and normallongitudinal variations but the doping profile is not formed to varyfrom a high concentration at one position substantially progressivelytoward a lower doping at a second position. Region 41 has an oppositedoping type than substrate 40. Preferably, substrate 40 is P-type andhas a resistivity of approximately eighty (80) Ohm-cm, and region 41 isN-type with a doping concentration of approximately 1E15 cm⁻³ to 2E15cm⁻³. Region 41 typically is about seven to eight (7-8) microns thick.Portions of region 41 form a portion of both transistors 18 and 19. Adrain contact 46 of transistor 18 is formed as a doped region on thesurface of substrate 40 and within region 41. Contact 46 is shaped as ahollow first circle having a first radius and a center 47. Contact 46 isformed concentric with region 41 and with a radius that is smaller thanthe radius of region 41. Because of the hollow circle shape of contact46, a first circular shaped inner portion of region 41 underlies contact46 (see FIG. 3). This first portion forms the drain region of transistor18. A second circular portion 42 of region 41 extends from the outercircumference of contact 46 to an outer edge 44 of region 41 and formsthe channel of transistor 18. The interface of substrate 40 with region41 functions as the gate of J-FET transistor 18. A third portion ofregion 41 adjacent to edge 44 and underlying at least a portion of gateconductor 54 generally is regarded as both the source of transistor 18and the drain of transistor 19. Typically substrate 40, and thus thegate of transistor 18, is connected to the lowest potential in thecircuit that uses device 10. Thus the drain and source of transistor 18are formed as closed geometric shapes with the source having a radiusthat is larger than the drain. Also, one doped region is used to formthe source and drain of transistor 18 and the drain of transistor 19.

A source region 49 of transistor 19 is formed as a doped region on thesurface of substrate 40 as an arc of a circle having a larger radiusthan the radius of the drain of transistor 19. Typically, an innerportion of source region 49 underlies gate conductor 54. A doped regionis formed within source region 49 to function as a source contact 50 oftransistor 19. Note that source region 49 and contact 50 arediscontinuous at a tap opening 70 of device 10 (See FIG. 2), thus,region 49 and contact 50 are an arc of a circle. A contact region 63 isformed as a doped region in substrate 40 external to transistors 18 and19. Contact region 63 is used to connect one end or terminal of resistor13 to substrate 40. A body region 48 of transistor 19 is formed as adoped region on the surface of substrate 40 underlying gate conductor54. Preferably, substrate 40, body region 48, and contact region 63 areP-type material, and region 41, source region 49, and contact 50 areN-type material in order to form transistor 18 as an N-channel J-FET andtransistor 19 as N-channel MOS transistors.

A gate insulator 52 is formed on substrate 40 overlying region 48 and atleast an inner edge of region 49. Typically, insulator 52 is thinsilicon dioxide, generally no greater than about fifty to sixty (50-60)nano-meters, in order to facilitate operation of transistor 19. Athicker insulator 53 is formed on substrate 40 overlying portion 42 andunderlying contact 61. Typically, contact 61 is connected to terminal 23of FIG. 1. Insulator 53 generally is at least about ten to thirty(10-30) times thicker than insulator 52 in order to assist in providinga high breakdown voltage between resistors 12 and 13 and the underlyingsilicon structure. Insulator 53 generally is no less than about one totwo (1-2) microns thick. Gate conductor 54 is formed to overlie at leasta portion of insulator 52. As conductor 54 is formed, the material usedfor conductor 54 is also formed on insulator 53 and then patterned toform a spiral pattern as illustrated in FIGS. 2 and 3. The spiralpattern forms resistors 12 and 13. Typically, the material used forconductor 54 is polysilicon. The portion of the polysilicon used to formresistors 12 and 13 may be doped differently or the same as conductor 54to provide a resistivity that provides the desired values for resistors12 and 13, and for conductor 54. In one embodiment, the polysilicon usedfor resistors 12 and 13 has a sheet resistance of no less than abouttwenty ohms/sq. Alternately, the material used for resistors 12 and 13can be formed separately from conductor 54. The spiral pattern is formedto make as many revolutions as possible around center 47 in order toprovide a high resistance for resistors 12 and 13. Using at least aminimum spacing between adjacent portions of the spiral pattern reducesthe electric field between the adjacent portions of the pattern. In oneexemplary embodiment, the spiral pattern has about thirty five (35)revolutions. Typically the spacing between adjacent revolutions of thespiral pattern is about one to two (1-2) microns. Other patterns can beused to form resistors 12 and 13. For example the pattern can be shapedas ellipses, squares, pentagons, hexagons, etc. especially if theunderlying region 41 has such a shape. Another insulator 57, such as aninter-layer dielectric, is applied to cover resistors 12 and 13,conductor 54, and portions of substrate 40 that are external totransistors 18 and 19. Using the minimum spacing between adjacentportions of the spiral pattern also reduces the lateral electric fieldacross insulator 57 that separates the adjacent portions of the spiralpattern thereby reducing the possibility of breakdown and increasing thevalue of the voltage that can be sensed by element 11. It should benoted that insulator 57 is not illustrated in FIG. 2 for clarity of thedrawings. A conductor 35 is formed through an opening in insulator 57 toelectrically contact the spiral pattern and form the pattern intoresistor 12 and 13. Another conductor 64 is formed through anotheropening in insulator 57 to electrically contact the distal end of thespiral and to connect one end or terminal of resistor 13 to substrate 40through contact region 63. Another conductor 59 is formed through anopening in insulator 57 overlying contact 50 to form electrical contactthereto to form a source conductor of device 10. Contact 61 may beformed as part of forming conductors 35, 59, and 64 or may be formedsubsequently. It should be noted that conductor 59 is not illustrated inFIG. 2 for clarity of the drawings.

Referring to FIG. 2, at the place where one of the revolutions of thespiral of element 11 passes opening 70, a conductor 35 is formed toextend over conductor 54 and out through opening 70 to form output 16.Output 16 can then be connected to other electrical elements (not shown)that are formed on substrate 40 such as an operational amplifier or acomparator. Conductor 35 extends out past the outside of transistor 19to facilitate forming electrical contact to elements external to device10. Conductor 64 is formed to electrically contact the distal end of thespiral and to connect one end or terminal of resistor 13 to substrate 40through contact region 63 (FIG. 3). A portion of gate conductor 54 isformed to also extend through opening 70 and form a tab 71 thatfacilitates making contact to gate conductor 54. Resistor 21 is formedas a doped region on the surface of substrate 40 external to device 28.One end of resistor 21 extends under tab 71, illustrated by dashedlines, to make electrical contact to region 41 at edge 44 and at node20. A second end of resistor 21 is connected to tab 71 by a metalconnection 72. A portion of region 48 extends through opening 70 tofacilitate forming contact to region 48. For clarity of the drawings,the extension of region 48 through opening 70 is not shown.

In operation, the J-FET functionality of transistor 18 acts to evenlydistribute the high voltage electric field that is imposed between thedrain and source of transistor 18 throughout region 41 and particularlyregion 42. Consequently, the impact of the high voltage electric fieldon resistors 12 and 13 is negligible in both the on or off states oftransistor 18. The converse is also true. The evenly distributedpotential throughout resistors 12 and 13 has negligible impact on theunderlying doped regions of transistor 18. Substrate 40 typically isconnected to the lowest voltage in the system that uses device 10. Whenthe high input voltage is applied to input 23, the large voltagedifference between substrate 40 and region 41 causes transistor 18 tosubstantially deplete of carriers. Such depletion will exist both insubstrate 40 and portion 42 of transistor 18. The potential acrossportion 42 as a result of the high input voltage will generally causeregion 42 to be substantially depleted and transistor 18 will operate inthe pinch-off mode. The doping concentrations of substrate 40 and region41 are selected to be low enough to provide the substantial depletion atthe voltages that are applied to input 23. In most embodiments, avoltage of greater than about five volts (5 V), typically greater thanabout forty to fifty volts (40V-50V), is applied to input 23 andpreferably about four hundred to seven hundred volts (400-700 V) isapplied. The combined depletion effects of substrate 40 and region 42can easily support such high voltages simply by extending theirdepletion widths without exceeding the critical electric field ofsilicon which is about 0.3 MV/cm.

The vertical voltage potential between element 11 and the top surface ofunderlying region 42 at any given location is mainly supported by thethickness of insulator 53 although a small portion of the verticalvoltage may be supported by the material used for element 11. Since ahigh voltage is applied to region 42 and a high voltage is also appliedto one terminal of resistor 12, only a moderate difference between thesevoltages remains to be supported vertically across insulator 53 andelement 11. The thickness of insulator 53 sustains the majority of thevertical voltage while retaining the electric field much lower than thebreakdown field of the material of insulator 53. Typically the materialis silicon dioxide and the resulting breakdown field of the material isabout 10 MV/cm. Only a small portion of the vertical voltage istypically supported by element 11 due to the low resistivity of thematerial. The material typically is doped polysilicon that has a dopingconcentration no less than about 1×10¹⁸ to 1×10⁹ atoms/cm³. For example,the vertical voltage across element 11 and insulator 53 may be aboutsixty to seventy volts (60-70V) for an applied voltage of about sevenhundred volts (700V) at input 23. Generally less than about one volt ofthis sixty to seventy volt vertical voltage is dropped vertically acrosselement 11 and the remainder is dropped across insulator 53.Generally,the voltage potential of each point on the pattern of resistors 12 and13 and at a corresponding point of underlying region 42 will almosttrack each other in potential. This assists in minimizing the value ofthe vertical electric field therebetween. The value of the verticalvoltage that can be sustained can be changed by adjusting the positionof the two ends of resistor 11 on insulator 53 relative to the portionsof transistor 18 such as contact 46 and edge 44. Since at least portion42 is substantially depleted of carriers, region 41 provides isolationbetween substrate 40 and element 11. Consequently, the high electricfield does not cause breakdown to substrate 40. Thus, region 41 andinsulator 53 assist in the operation of element 11. Those skilled in theart will realize that all carriers are not depleted from portion 42under all operating conditions, but that most of the carriers aredepleted and under such conditions the region is referred to as a regionthat is depleted of carriers or a depletion region or substantiallydepleted of carriers. Those skilled in the art also realize that element11 and associated resistors 12 and 13 may be formed to overlie othersuch depletion regions and not just a depletion region of a J-FET.

FIG. 4 schematically illustrates a circuit diagram of an embodiment of adevice 30 that is an alternate embodiment of device 10 of FIG. 1. Device30 includes a high voltage sense element 32 that is an alternateembodiment of element 11. Element 32 receives the high voltage and formsthe sense signal on sense output 16. One terminal of resistor 13 extendsoutside of the active area of device 28 and forms a connection terminal14. Device 30 includes a power saving switch 22 that is used toselectively switch terminal 14 to the lowest voltage that is applied toelement 32. Switch 22 includes a switch control input 17 that is used toenable or disable switch 22. For example, switch 22 can be enabledperiodically to form the sense signal on output 16 and then disabledafter the value of the sense signal has been used. Disabling switch 22reduces the amount of power dissipated by element 32 and still allowselement 32 to form the sense signal similarly to element 11.

FIG. 5 illustrates an enlarged cross-sectional view of an embodiment ofa portion of a semiconductor device 150 that includes element 11. Device150 is formed on a semiconductor substrate 140 that is similar tosubstrate 40 of FIGS. 2 and 3. A doped region 141 is formed on a surfaceof substrate 140. The doping and isolation characteristics of region 141are similar to region 41. A contact 161 is formed to receive the highinput voltage. Contact 161 is also formed to contact one terminal ofresistor 12 and to provide a connection to region 141. Thus, the highvoltage received by contact 161 is applied to region 141. A contactregion 163 is formed in substrate 140 similarly to region 63. A secondend or terminal of resistor 13 is extended across insulator 53 to makeelectrical contact to region 163. Similarly to element 11, region 141and insulator 53 are a portion of element 32. Device 150 can be part ofa pulse width modulated (PWM) power supply controller or other type ofdevice that may utilize element 11 to sense the continuously variablevalue of a high voltage signal.

FIG. 6 schematically illustrates a circuit diagram of an embodiment of aportion of a high voltage semiconductor device 80 that is an alternateembodiment of device 10. Element 11 includes resistor 12 but omitsresistor 13. One terminal of resistor 12 is connected to receive thehigh input voltage and a second terminal is connected to output 16 tosupply the low voltage sense signal. Similar to device 10, the value ofresistor 12 is selected to be large in order to minimize the powerdissipated by element 11 and typically is no less than about fifteen(15) meg-ohms.

Device 80 also includes a current mirror configured to receive the sensesignal and responsively form an output voltage on an output 88 that isrepresentative of the high input voltage received on input 23. Thecurrent mirror includes a clamp diode 81, a comparator transistor 84,and a current source 85. Output 88 is formed by the connection oftransistor 84 and current source 85. Diode 81 clamps the voltage on thelow voltage terminal of resistor 12 and at the base of transistor 84 toa fixed voltage. Terminal 86 of the current mirror generally isconnected to receive an operating voltage that is derived from thevoltage on output 24. As the value of the voltage on input 23 increases,the value of a current 82 that flows through resistor 12 also increases.The increase in current 82 enables transistor 84 to conduct more currentand reduces the voltage on output 88. Thus, as the value of the highinput voltage on input 23 increases, the value of the sense signal onoutput 88 responsively decreases and functions as a comparator outputthat switches states when the current through resistor 12 becomes morethan the current in current source 85. It will be appreciated thatsource 85 may be replaced by a resistor and that output 88 would thengenerate an analog voltage representative of a value of the voltagereceived on input 23.

FIG. 7 illustrates an enlarged plan view of a portion of an embodimentof device 80 explained in the description of FIG. 6. This descriptionhas references to both FIG. 6 and FIG. 7. The portion of device 80illustrated in FIG. 7 omits the current mirror of device 80. Similarlyto device 10, resistor 12 is formed to overly a portion of J-FET 18 thatis substantially depleted of carriers during the operation of transistor18. Since resistor 13 is omitted from device 80, the pattern of resistor12 typically is extended to include the pattern used for resistor 13 inFIG. 2 and FIG. 3. Note that one terminal of resistor 12 is connected toreceive the high input voltage from input 23 and the other terminal ofresistor 12 is connected to output 16 and not connected to a currentcarrying electrode of transistor 18 or 19.

FIG. 8 schematically illustrates a portion of an embodiment of a powersupply control system 100 that utilizes device 10 to regulate the valueof an output voltage of system 100. System 100 receives a bulk inputvoltage between input terminals 110 and 111 and controls a power switch105 to provide an output voltage between output terminals 112 and 113.Device 10 receives the bulk voltage on input 23 and provides the sensesignal on output 16. A power supply control system 101 of system 100 hasa PWM controller 103, a control circuit 102, and device 10. Device 10 isalso used to provide a start-up voltage for operating controller 103 andcircuit 102. An amplifier 104 receives the sense signal, amplifies it.Circuit 102 receives the amplified sense signal and processes it toprovide control functionality for controller 103. The controlfunctionality could include, among other functions, line under-voltagedetection and shutdown, line over-voltage detection and shutdown, inputpower determination and limitation, line feed-forward for current moderamp compensation, power limiting, and/or standby operation. Thoseskilled in the art will appreciate that devices 30, 80, or 150 couldalso be used instead of device 10.

In another embodiment, node 23 may be connected to the drain of switch105 instead of input 110 and the amplified sense signal could be used bycontrol circuit 102 to regulate the output voltage as a function of thetransformer flyback voltage when switch 105 is not conducting. Controlcircuit 102 could also sense the flyback voltage when switch 105 is notconducting to determine whether or not any energy remains in thetransformer at some point in time.

In view of all of the above, it is evident that a novel device, methodof forming the device, and method of using the device is disclosed.Included, among other features, is forming a high voltage elementoverlying a doped region that can be substantially depleted of carriersduring the operation of the high voltage element. Also included isforming the high voltage element overlying a thick insulator, such as afield oxide, that is overlying a portion of the doped region. The word“connected” is used throughout for clarity of the description, however,it is intended to have the same meaning as the word “coupled”.Accordingly, “connected” should be interpreted as including either adirect connection or an indirect connection.

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 12. A high voltage element comprising: a substrate of asemiconductor material having a first conductivity type; a firsttransistor having a first doped region of a second conductivity type ona first portion the substrate; an insulator overlying a portion of thefirst doped region; and a first resistor formed overlying at least aportion of the insulator and a first portion of the first doped region,a first terminal of the first resistor devoid of a connection to acurrent carrying electrode of the first transistor.
 13. The high voltageelement of claim 12 further including a second resistor overlying theinsulator, overlying a second portion of the first doped region, andcoupled to the first terminal of the first resistor.
 14. The highvoltage element of claim 12 wherein a second terminal of the firstresistor is coupled to a current carrying electrode of the firsttransistor.
 15. The high voltage element of claim 12 wherein of thefirst terminal of the first resistor is coupled to a switch.
 16. Thehigh voltage element of claim 12 wherein the insulator has a thicknessof approximately 500 to 2000 nano-meters.
 17. The high voltage elementof claim 12 wherein the first resistor is coupled to operably receive avoltage that is greater than about five volts.
 18. (canceled) 19.(canceled)
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 30. A method of sensing a high voltagecomprising: providing a semiconductor substrate; forming a doped regionon the semiconductor substrate; forming a sense element overlying aportion of the semiconductor substrate and overlying a portion of thedoped region; and configuring the sense element to receive a highvoltage having a value that is greater than approximately forty voltsand responsively form a sense signal having a value that isrepresentative of the value of the high voltage and varies in acontinuous manner over an operating range of the value of the highvoltage wherein a first terminal of the sense element is not coupled tothe doped region.
 31. The method of claim 30 wherein forming the senseelement includes forming a resistor that receives the high voltage onthe first terminal and forms the sense signal on a second terminal ofthe resistor.
 32. The method of claim 30 wherein forming the senseelement on the semiconductor substrate includes coupling a secondterminal of the first resistor to a circuit external to the high voltageelement and not connected directly to the high voltage element.
 33. Themethod of claim 30 wherein forming the sense element overlying theportion of the semiconductor substrate includes forming a insulatoroverlying a portion of the doped region and forming the sense elementoverlying a portion of the insulator.
 34. The method of claim 33 whereinforming the insulator includes forming the sense element overlying aportion of a transistor.
 35. The method of claim 30 wherein forming thesense element includes forming the sense element overlying a portion ofa J-FET.
 36. The method of claim 30 wherein forming the sense elementoverlying the portion of the semiconductor substrate includesconfiguring the sense element to receive the high voltage that isgreater than one hundred volts.
 37. The method of claim 30 whereinforming the sense element overlying the portion of the semiconductorsubstrate includes configuring the sense element to receive the highvoltage that is greater than four hundred volts.
 38. The method of claim30 wherein configuring the sense element to receive the high voltagehaving the value that is greater than approximately forty volts andresponsively form the sense signal includes configuring the senseelement to form one of a voltage having a value that is representativeof the high voltage or a current having a value that is representativeof the high voltage.
 39. The method of claim 30 wherein configuring thesense element to receive the high voltage having the value that isgreater than approximately forty volts and responsively form the sensesignal includes configuring a circuit to use the sense signal for one ofdetecting a line under-voltage condition, detecting a line over-voltagecondition, determining input power, limiting input power, powerlimiting, controlling standby operation, or a line feed-forward functionfor current mode ramp compensation.
 40. The method of claim 30 whereinconfiguring the sense element to receive the high voltage having thevalue that is greater than approximately forty volts and responsivelyform the sense signal includes configuring a circuit to use the sensesignal for one of regulating an output voltage or detecting an energytransfer state of an energy storage element.
 41. A method of sensing ahigh voltage comprising: providing a semiconductor substrate; forming adoped region on the semiconductor substrate; forming a sense elementoverlying at least a portion of the doped region; and configuring thesense element to receive a high voltage having a value that is greaterthan approximately forty volts and responsively form a sense signalhaving a value is representative of the value of the high voltagewherein one terminal of the sense element is not connected to the dopedregion.
 42. The method of claim 41 further including configuring thesense element to form the sense signal to vary in a continuous mannerover an operating range of the value of the high voltage.
 43. The methodof claim 41 further including forming an insulator overlying the dopedregion and positioned between a resistor and the doped region.
 44. Themethod of claim 41 wherein forming the doped region includes forming thedoped region as a portion of a JFET.
 45. The method of claim 41 furtherincluding coupling a circuit to receive the high voltage commonly withthe sense element and responsively provide a current.
 46. A method offorming a high voltage sense element comprising: forming a semiconductordevice on a semiconductor substrate wherein the semiconductor device hasat least one high voltage input terminal; forming a sense elementoverlying at least a portion of the semiconductor substrate; andconfiguring the sense element to receive a high voltage from the highvoltage input terminal and responsively form a sense signal having avalue that is representative of the value of the high voltage whereinthe value of the high voltage is greater than approximately forty volts;and operably coupling a first circuit to use the sense signal for one ofdetecting a line under-voltage condition, detecting a line over-voltagecondition, determining input power, limiting input power, powerlimiting, controlling standby operation, a line feed-forward functionfor current mode ramp compensation, regulating an output voltage, ordetecting an energy transfer state of an energy storage element.
 47. Themethod of claim 46 further including operably coupling a second circuitto use the sense signal for a different one of detecting a lineunder-voltage condition, detecting a line over-voltage condition,determining input power, limiting input power, power limiting,controlling standby operation, a line feed-forward function for currentmode ramp compensation, regulating an output voltage, or detecting anenergy transfer state of an energy storage element wherein the differentone is not performed by the first circuit.
 48. The method of claim 46wherein forming the semiconductor device on a semiconductor substrateincludes forming a doped region on the semiconductor substrate, formingthe sense element overlying at least a portion of the doped regionwherein a first terminal of the sense element is not coupled to thedoped region.
 49. The method of claim 46 wherein forming thesemiconductor device on a semiconductor substrate includes forming adoped region on the semiconductor substrate, forming the sense elementoverlying at least a portion of the doped region wherein a firstterminal of the sense element is not coupled to the doped region.